FPGA design of the fast decoder for burst errors correction / E. A. Mytsko [et al.]
Уровень набора: (RuTPU)RU\TPU\network\3526, Journal of Physics: Conference SeriesЯзык: английский.Резюме или реферат: The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns..Примечания о наличии в документе библиографии/указателя: [References: 20 tit.].Тематика: электронный ресурс | труды учёных ТПУ | дизайн | декодеры | коррекция | ошибки | передача данных | полиномы | ПЛИС | производительность Ресурсы он-лайн:Щелкните здесь для доступа в онлайн | Щелкните здесь для доступа в онлайнTitle screen
[References: 20 tit.]
The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns.
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