Finding False Paths in Sequential Circuits / A. Yu. Matrosova, V. V. Andreeva, S. V. Chernyshov [et al.]

Уровень набора: Russian Physics JournalАльтернативный автор-лицо: Matrosova, A. Yu., Anzhela Yurjevn;Andreeva, V. V., Valentina Valerjevna;Chernyshov, S. V., Semen Vladimirovich;Rozhkova, S. V., mathematician, Professor of Tomsk Polytechnic University, Doctor of Physical and Mathematical Sciences, 1971-, Svetlana Vladimirovna;Kudin, D. V., Dmitry ValerjevichКоллективный автор (вторичный): Национальный исследовательский Томский политехнический университет, Школа базовой инженерной подготовки, Отделение математики и информатикиЯзык: английский ; резюме, eng.Резюме или реферат: Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed..Примечания о наличии в документе библиографии/указателя: [References: 7 tit.].Аудитория: .Тематика: электронный ресурс | труды учёных ТПУ | sequential circuit | reduced ordered binary decision diagram (ROBDD) | false path | equivalent normal form | path delay fault Ресурсы он-лайн:Щелкните здесь для доступа в онлайн
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[References: 7 tit.]

Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.

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