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035 _a(RuTPU)RU\TPU\network\38451
090 _a667246
100 _a20220310a2018 k y0engy50 ba
101 0 _aeng
_deng
135 _adrcn ---uucaa
181 0 _ai
182 0 _ab
200 1 _aFinding False Paths in Sequential Circuits
_fA. Yu. Matrosova, V. V. Andreeva, S. V. Chernyshov [et al.]
203 _aText
_celectronic
300 _aTitle screen
320 _a[References: 7 tit.]
330 _aMethod of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.
333 _aРежим доступа: по договору с организацией-держателем ресурса
461 _tRussian Physics Journal
463 _tVol. 60, iss. 10
_v[P. 1837-1844]
_d2018
610 1 _aэлектронный ресурс
610 1 _aтруды учёных ТПУ
610 1 _asequential circuit
610 1 _areduced ordered binary decision diagram (ROBDD)
610 1 _afalse path
610 1 _aequivalent normal form
610 1 _apath delay fault
701 1 _aMatrosova
_bA. Yu.
_gAnzhela Yurjevn
701 1 _aAndreeva
_bV. V.
_gValentina Valerjevna
701 1 _aChernyshov
_bS. V.
_gSemen Vladimirovich
701 1 _aRozhkova
_bS. V.
_cmathematician
_cProfessor of Tomsk Polytechnic University, Doctor of Physical and Mathematical Sciences
_f1971-
_gSvetlana Vladimirovna
_2stltpush
_3(RuTPU)RU\TPU\pers\34139
701 1 _aKudin
_bD. V.
_gDmitry Valerjevich
712 0 2 _aНациональный исследовательский Томский политехнический университет
_bШкола базовой инженерной подготовки
_bОтделение математики и информатики
_h8031
_2stltpush
_3(RuTPU)RU\TPU\col\23555
801 2 _aRU
_b63413507
_c20220310
_gRCR
856 4 _uhttps://doi.org/10.1007/s11182-018-1290-0
942 _cCF